Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.

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There are 6 parts and a bonus. Remember to ground the CH – terminals. We will now need to construct another D-latch that will serve as slave latch to form our master-slave D Flip-flop as shown in Figure 8 Click on the Figure to view a full-size picture. What to do in the lab report Submit all screen shots. We will use the D-latch constructed in the previous section as the master latch in our master slave D flip flop.

The CD is a very versatile IC with many uses. You should see that DIO8 is also low. Because the output of the first inverter is now zero, the capacitor will begin to discharge through R1, and the opposite side will be charged. Your output should look similar to figure Construct 3 inverters using a CD by making the following connections: A steady low should appear inspite of changing D to logic High since the previous value at D-input was low.


You should take a total of three screenshots, one each, corresponding to each inverter output. You can also document mistakes or missteps that occurred, e. Estimate Vtn from Ids-Vgs curves. Schematic of D latch. The output of the first inverter will be Vdd and the output of the second inverter will be zero. Experiment with different values of C1 and R1 and try to determine their relationship to the frequency of the output.

Measure the Ids-Vds curves for a multiple Vgs values. The two inverters can be built from a CD by making the following connections: Pin diagram of ALD package.


The other two pairs are more general purpose. A circuit symbol description of the two pairs of transistors from the data sheet is shown below in figure 1. Consider the circuit shown in figure Construct the circuit shown in figure You should see 3 waveforms similar to the one shown in figure 3.

What to do in the lab report Attach screen shots for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete. Groups of pins that are not connected are separated by a semicolon.

That is going to be left as a bonus exercise. You should see a graph similar to the one shown below in figure 4. Schematic of D flip flop. Schematic of D latch. Adjust frequency until you can cd datasheet a clear rise and fall of the output signal.

For the complete circuit you will need fd CD chips. Compare measured Vdsat with 1st order theory, i. D is transmitted to the output Q through the first transmission gate and the two-inverter cascade.


Clean up Previous topic 7. First, assume the voltage at the input to the first inverter is zero. Output of cd datasheet inverter.

Fairchild Semiconductor

Remove all the connections to the ALD chip shown in the dashed box cd datasheet Figure 3. This is the transparent phase of the latch.

Draw an cd circuit for the following wiring description using a CD What to do in lab report Show datasheeg screen shots of inverter outputs. Output of second inverter.

Have your GTA sign off on datasehet part before proceeding to the next part. You can download or view the data sheet cd datasheet or here. You do not have to draw a gate level schematic if you can determine the logic function implemented.

CD Datasheet Texas Instruments pdf data sheet FREE from

Connect pins 2,9 to CH0, and pins 4,11 to CH1. You should see a graph similar to the one shown below in figure cd datasheet.

The CD includes diodes to protect it from static discharge, but it can still be damaged if it is not handled carefully.